1. Field of the Invention
The present invention relates to a multiple value type semiconductor memory device, and more particularly to reading system of the multiple value type non-volatile memory device.
2. The Related Art
FIG. 6 is a structural view of a conventional three-stage reading method circuit. FIG. 7 is a data read timing view of the circuit shown by FIG. 6.
Suppose that Vt1 is set to a memory cell C1 (206) out of four threshold values Vti (i=b 1, 2, 3 or 4, Vt0&lt;Vt1&lt;Vt2&lt;Vt3). However, here the threshold value Vti reference to a voltage between a source and a gate in which a drain current of the cell exceeds a leak current level in the off state. The threshold value of the reference cell Rc2 (208) is set to Vt1 and the threshold value of the reference cell Rc3 (209) is set to Vt2 respectively.
An output level of a regulated voltage circuit 1 (218) is the same voltage as the threshold value Vt0. An output level of a regulated voltage circuit 2 (219) is set to the threshold value Vt1. An output level of the regulated voltage circuit 3 (220) is set to the same voltage as the threshold value Vt2. Consequently, in the case where the output level Vt0 of the regulated voltage circuit 1 (218) is given to the gate of the memory cell, the threshold value which is set in the memory cell is other than Vt0 (Vt1, Vt2 or Vt3), the memory cell is set to an OFF state. In the case where the output level Vt1 of the regulated voltage circuit 2 (219) is given to the gate of the memory cell, the memory cell, the threshold value which is set in the memory cell is Vt2 or Vt3, is set to the OFF state. In the case where the output level Vt2 of the regulated voltage circuit 3 (220) is given to the gate of the memory cell, the memory cell, the threshold value which is set in the memory cell is Vt3, is set to the OFF state. First stage word line level which is an output of regulated voltage circuit 1 is given to the transistor RC1. A second stage word line level which is an output from the regulated voltage circuit 2 is given to the gate of the transistor RC2. A third stage word line level which is an output from the regulated voltage circuit 3 is given to the gate of the transistor RC3. Each drains of reference cells 1 through 3 are connected to the reference amplifier 1 (203), a reference amplifier 2 (204) and a reference amplifier 3 (205), respectively.
Next, the operation of the conventional three stage reading current is explained.
A pulse generating circuit 217 generates a pulse signal (231),/P1 (232), a P2 (235),/P3 (236),(Here, symbol"/" denotes a negative logic).
In the beginning, in the case where all the pulse signal P1 (231), a P2 (233), a P3 (235) are set to H level, this circuit is in an inactive state.
Next, when the word line selection signal XP (230) and a pulse signal P1 (231) become a L level (Tac 1 period). Since a transfer gate 240 and a transfer gate 243 is turned on to be set in a conductive state, and a transfer gate 246 is also turned on to be set in a conductive state with XP signal 230, an output level Vt0 of the regulated voltage circuit 1 is supplied through a word line W00 (250) (first stage word level) to the gate of the memory cell C1. Therefore, the memory cell C1 is being selected.
Here, since the threshold voltage Vt1 is set in the memory cell C1 (206), the memory cell C1 (206) is set in the OFF state. On the other hand, the threshold value of a reference cell RC1 (207) is set to Vt0, so that the reference cell RC1 (207) is set in the ON state. With a comparison of the threshold value with the reference voltage, it is made clear that the data at a timing Tac1 is OFF (High, for example, logic value 1).
Next, a pulse signal P1 (231) is risen, and P2 (233) is fallen so that the transfer gate 240 and the transfer gate 243 are set in a non-conductive state, the transfer gate 241 and the transfer gate 244 are set in the conductive state at Tac2 period.
At this time, the output level Vt1 of the regulated voltage circuit 2 is supplied through the word line W00 (233) (second stage word level) to the memory cell C1, the memory cell C1 (206) is set to the ON state, and the reference cell RC2 (208) is also set in the ON state, and it is judged that the data at a timing Tac2 is set to the ON state (Low, for example, logic value 0).
Next, the pulse signal P2 (233) is risen, and the pulse signal P3 (235) is fallen so that the transfer 241 and the transfer gate 244 are set in the non-conductive state while the transfer gate 242 and the transfer gate 245 are set to a conductive state at Tac2 and Tac3, respectively.
At time period Tac 3, an output level Vt2 of the regulated voltage circuit 3 is supplied through the word line W00 (250) (third stage level) to the memory cell C1 so that the memory cell C1 (206) is set in the ON state. The reference cell RC3 (209) is also set in the ON state. In the case of the same gate level, it is judged that the data at Tac3 is ON (Low, for example, logic value 0).
Relation between the output of the (differential) sense amplifier 202 at time Tac1, Tac2, Tac3 and an output D0 and D1 of the output circuit 214 with respect to each threshold values is as shown in Table 1.
TABLE 1 ______________________________________ Tac 1 Tac 2 Tac 3 D1 D0 ______________________________________ Vt0 0 0 0 0 0 Vt1 1 0 0 0 1 Vt2 1 1 0 1 0 Vt3 1 1 1 1 1 ______________________________________
This methods has advantage in that ON and OFF of the transistor can be judged with the word line level and difference with the threshold voltage Vt written on the cell so that a secured reading can be carried out. However, there is a problem in that the access speed is slow. That is, in the case where a parasitic capacitance C and resistor R attached on the word line supplying signal X, time required for accumulate attainment of desired level V1 is represented approximately by the product of C and R. Consequently, speed in the case of reading the aforementioned word line in three stages can be represented by the following equation when the reading completion time from the determination of the level of the word line at the sense amplifier is set to Ts. EQU Tac=3.times.C.times.R+3.times.Ts.
In other words, in order to read and exchange the cell written in the 2 Bit data, time for reading the data will be three times as long as time for reading a normal 1 Bit. Consequently, market demand for a high speed devices is not satisfied, and only semiconductor memory devices of a special reading method such as serial access method or the like can be supplied to the market.
Special circuits such as a regulated voltage circuit for generating desired voltage level, a pulse generating circuit and a delay circuit for controlling a word line rise time are needed such that these special circuits occupy about 20% of the chip area.
Furthermore, in the case of the binary search style, as compared with the reading method shown in FIGS. 6 and 7, a second stage word level is generated in the Tac period in the beginning to supply to the memory cell so that it is judged whether the memory cell is turned on or off. When the memory cell is turned on, the word line level is set to the first stage word level lower than the second stage word level in the following Tac 2 period. When the memory cell is turned off, the word line level is set to the third stage word level higher than the second stage word level. As a result, the 2 Bit data is outputed by judging whether the memory cell is turned on and off during the Tac 2 period. However, the method cannot be used in the case where a plurality of selected memory cells are connected to one word line. That is, when one word line is connected to one memory cell having the threshold voltage Vt1 and an other memory cell having the threshold voltage Vt2, the aforementioned memory cell is turned on in Tac 1 period. Then, in the following Tac 2 period, the word line level must be set to the first stage word level to detect the threshold voltage of the aforementioned memory cell. However, since the latter memory cell is turned off in the Tac 1 period, the word line level must be set to the third stage word level in the Tac 2 period. Therefore, since this reading manner requires one word line corresponding to one memory cell to read out the data stored in the memory cells during Tac 1 and 2 period, a problem of chip size increased occurs.
On the other hand, with respect to the multiple value cell type semiconductor memory device, another method for reading data of the cell is by raising the word line at one-time as disclosed, for example, by the Japanese Laid-Open Patent application No. SHO 62-140298.
FIG. 8 shows a circuit for a semiconductor memory device described in the SHO 62-140298. In this example, this circuit comprises a reference amplifier RA10 for generating three reference voltage signals (here, this figure only shows a reference amplifier RA10 consisting of transistors S1 and S2 for the generating one reference voltage signal) and a sense amplifier SA10 consisting of transistors Q1, Q11, and Q12. A memory transistor M1 can be set to one of four different I.sub.on current levels (I1&lt;I2&lt;I3&lt;I4). On the other hand, reference currents (I1+I2, I2+I3, I3+I4) are formed with a combination of transistors S1, S2, S2+S3, S3+S4 from the transistors S1, S2, S3, and S4 having the respective I.sub.on current levels I1, I2, I3, and I4. Furthermore, the load MOS transistors Q11 and Q12 having the same size as the load MOS transistor Q1 of the sense amplifier, constitutes a current mirror pair. When the current which flows through the memory cell M1 is temporarily I2, the current which flows through the transistor Q1 becomes I2 so that the current which flows through the transistors Q11 and Q12 becomes 2.times.I2 in total. However, with the current which flows through the load MOS transistors Q11 and Q12 the relationship of 2.times.I2&gt;I1+I2, 2.times.I2&lt;I2+I3, 2.times.I2&lt;I3+I4 is established with the result that the output level becomes H only in the case of 2.times.I2&gt;I1+I2. In other cases, the current can be detected all as low.
In the aforementioned embodiment, when the memory cell transistor M1 may be alternative currents I1 or I2, the reference current I1+I2 is generated as the reference current to compare with the current flowing in the cell transistor M1.
In this case, when this embodiment is compared with the previous embodiment, there is an advantage in that it becomes possible to read the data written in the memory cell and to carry out a high speed operation. However, a cell current I.sub.on in the memory cell area has a large variation so that the reading operation becomes inaccurate. Further, two reference cells are required with respect to one reference amplifier as a reference cell so that the area of the chip occupied by the reference cell becomes large. That is, it is difficult in the process to control the variation of current I.sub.on with a slight difference in a slight threshold value to write data on the memory cell, and data writing becomes unreliable with respect to the cell I.sub.on variation. Further, the reference cell area will increase. Moreover, two references are required to produce one comparison value so that a distribution of errors is doubled so as to produce and unreliable readings as a result of variation of the cell current I.sub.on.